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MRF89XA
4.8 General PCB Layout Design
The following guidelines can be used to assist in high-
frequency PCB layout design.
The printed circuit board is usually comprised of two or
four basic FR4 layers.
The two-layer printed circuit board has mixed signal/
power/RF and common ground routed in both the lay-
ers (see Figure 4-8 ).
The four-layer printed circuit board (see Figure 4-9 ) is
comprised of the following layers:
? Signal layout
? Thorough decoupling on each power pin is
beneficial for reducing in-band transceiver noise,
particularly when this noise degrades performance.
Usually, low value caps (27-47 pF) combined with
large value caps (100 nF) will cover a large
spectrum of frequency.
? Passive component (inductors) should be in the
high-frequency category and the Self-Resonant
Frequency (SRF) should be at least two times
higher than the operating frequency.
? The additional trace length affects the crystal
oscillator by adding parasitic capacitance to the
overall load of the crystal. To minimize this, place
?
?
RF ground
Power line routing
the crystal as close as possible to the RF device.
? Setting short and direct connections between the
? Common ground
The following guidelines explain the requirements of
the previously mentioned layers:
? It is important to keep the original PCB thickness,
because any change will affect antenna perfor-
mance (see total thickness of dielectric) or
microstrip lines’ characteristic impedance.
? For good transmit and receive performance, the
trace lengths at the RF pins must be kept as short
as possible. Using small, surface mount compo-
nents (in 0402/0603 package) yields good perfor-
mance and keeps the RF circuit small. RF
connections should be short and direct.
? Except for the antenna layout, avoid sharp corners
because they can act as an antenna. Round corners
will eliminate possible future EMI problems.
? Digital lines are prone to be very noisy when han-
dling periodic waveforms and fast clock/switching
rates. Avoid RF signal layout close to any of the
digital lines.
? A VIA filled ground patch underneath the IC
transceiver is mandatory.
? The power supply must be distributed to each pin in
a star topology, and low-ESR capacitors must be
placed at each pin for proper decoupling noise.
components on board minimizes the effects of
“frequency pulling” that might be introduced by stray
capacitance. It even allows the internal load capaci-
tance of the chip to be more effective in properly
loading the crystal oscillator circuit.
? Long run tracks of clock signal may radiate and
cause interference. This can degrade receiver per-
formance and add harmonics or unwanted
modulation to the transmitter.
? Keep clock connections as short as possible and
surround the clock trace with an adjacent ground
plane pour. Pouring helps in reducing any radiation
or crosstalk due to long run traces of the clock
signal.
? Low value decoupling capacitors, typically 0.01-0.1
μF, should be placed for V DD of the chip and for bias
points of the RF circuit.
? High value decoupling capacitors, typically 2.2-10
μF, should be placed at the point where power is
applied to the PCB.
? Power supply bypassing is necessary. Poor bypass-
ing contributes to conducted interference, which can
cause noise and spurious signals to couple into the
RF sections, significantly reducing the performance.
FIGURE 4-8:
TWO BASIC COPPER FR4 LAYERS
Signal/Power/RF and
Common Ground
Dielectric Constant = 4.5
Signal/Power/RF and
Common Ground
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 101
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